january 2009 ? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 mm745hc174 ? hex d-type flip-flops with clear mm74hc174 ? hex d-type flip-flops with clear features ? typical propagation delay: 16ns ? wide operating voltage range: 2v?6v ? low input current: 1a maximum ? low quiescent current: 80a (74hc series) ? output drive: 10 lsttl loads description the mm74hc174 edge-triggered flip-flops utilize silicon-gate cmos technology to implement d-type flip- flops. they possess high noise immunity, low-power, and speeds comparable to low-power schottky ttl circuits. this device contains six master-slave flip-flops with a common clock and common clear. data on the d input with the specified setup and hold times is transferred to the q output on the low-to-high transition of the clock input. when low, the input sets all outputs to a low state. each output can drive ten low-power schottky ttl equivalent loads. the mm74hc174 is functionally and pin comparable to the 74ls174. all inputs are protected from damage due to static discharge by diodes to v cc and ground. ordering information part number operating temperature range eco status package packing method mm74hc174m -40 to +85c tubes mm74hc174mx -40 to +85c rohs 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150 inch narrow tape and reel mm74hc174mtc -40 to +85c tubes mm74hc174mtcx -40 to +85c rohs 16-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide tape and reel mm74hc174n -40 to +85c rohs 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 inch wide tubes for fairchild?s definition of ?green? eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 2 mm74hc174 ? hex d-type flip-flop with clear pin configuration figure 1. pin configuration (top view) truth table (each flip-flop) inputs output clear clock d q low don?t care don?t care low high (1) high high high (1) low low high low don?t care q 0 (2) notes: 1. transition from low to high level. 2. the level of q before the indicated steady-state input conditions were established. logic diagram figure 2. logic diagram
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 3 mm74hc174 ? hex d-type flip-flop with clear absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. unless otherwise noted, all voltages are referenced to ground. symbol parameter min. max. unit v cc supply voltage -0.5 +7.0 v v in dc input voltage -1.5 to v cc +1.5 v v out dc output voltage -0.5 to v cc +0.5 v i ik , i ok clamp diode current 20 ma i out dc output current, per pin 25 ma i cc dc v cc or gnd current, per pin 50 ma t stg storage temperature range -65 +150 c tssop, pdip 600 p d power dissipation (3) soic 500 mw t l lead temperature, soldering10 seconds 260 c notes: 3. power dissipation temperature derating? pl astic ?n? package:12mw/c from 65 to 85c. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage 2 6 v v in , v out dc input or output voltage 0 v cc v t a operating temperature range -40 +85 c v cc =2.0v 1000 ns v cc =4.5v 500 ns t r , t f input rise and fall times v cc =6.0v 400 ns
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 4 mm74hc174 ? hex d-type flip-flop with clear dc electrical characteristics (4) t a =25c t a =-40 to+85c t a =-55 to +125c symbol parameter conditions v cc (v) typ. guaranteed limits units 2.0 1.5 1.5 1.5 4.5 3.15 3.15 3.15 v ih minimum high level input 6.0 4.2 4.2 4.2 v 2.0 0.5 0.5 0.5 4.5 1.35 1.35 1.35 v il minimum low level input 6.0 1.8 1.8 1.8 v 2.0 2.0 1.9 1.9 1.9 4.5 4.5 4.4 4.4 4.4 v in =v ih or v il , ? i out ? 20a 6.0 6.0 5.9 5.9 5.9 v in =v ih or v il , ? i out ? 4.0ma 4.5 4.20 3.98 3.84 3.70 v oh minimum high level output voltage v in =v ih or v il , ? i out ? 5.2ma 6.0 5.70 5.48 5.34 5.20 v 2.0 0 0.1 0.1 0.1 4.5 0 0.1 0.1 0.1 v in =v ih or v il , ? i out ? 20a 6.0 0 0.1 0.1 0.1 v in =v ih or v il , ? i out ? 4.0ma 4.5 00.2 0.26 0.33 0.40 v ol minimum low level output voltage v in =v ih or v il , ? i out ? 5.2ma 6.0 0.20 0.26 0.33 0.40 v i in maximum input current v in =v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current v in =v cc or gnd, i out =0a 6.0 8 80 160 a note: 4. for a power supply of 5v 10%, the worst-case output voltages (v oh and v ol ) occur for hc at 4.5v. the 4.5v values should be used when designing with this supply. worst-case v ih and v il occur at v cc = 5.5v and 4.5v, respectively. (the v ih value at 5.5v is 3.85v.) the worst-case leakage current (i in , i cc , and i oz ) occurs for cmos at the higher voltage, so the 6.0v values should be used.
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 5 mm74hc174 ? hex d-type flip-flops with clear ac electrical characteristics v cc = 5v, t a = 25c and c l = 15pf, t r = t f = 6ns. symbol parameter typ. guaranteed limit unit f max maximum operating frequency 50 30 mhz t phl ,t plh maximum propagation delay, clock, or clear to output 16 30 ns t rem minimum removal time, clear to clock -2 5 ns t s minimum setup time, data to clock 10 20 ns t h minimum hold time, clock to data 0 5 ns t w minimum pulsewidth, clock or clear 10 16 ns ac electrical characteristics (5) c l = 50pf, t r = t f = 6ns unless otherwise noted. t a =25c t a =-40 to+85c t a =-55 to +125c symbol parameter v cc (v) typ. guaranteed limits units 2.0 5 4 3 4.5 27 21 18 f max maximum operating frequency 6.0 31 24 20 mhz 2.0 55 165 206 248 4.5 18 33 41 49 t phl ,t plh maximum propagation delay, clock, or clear to output 6.0 16 28 35 42 ns 2.0 1 5 5 5 4.5 1 5 5 5 t rem minimum setup time, data to clock 6.0 1 5 5 5 ns 2.0 42 100 125 150 4.5 12 20 25 30 t s minimum setup time, data to clock 6.0 10 17 21 25 ns 2.0 1 5 5 5 4.5 1 5 5 5 t h minimum hold time, clock to data 6.0 1 5 5 5 ns 2.0 35 80 106 120 4.5 10 16 20 24 t w minimum pulse width, clock or clear 6.0 8 14 18 20 ns 2.0 30 75 95 110 4.5 8 15 19 22 t tlh ,t thl maximum output rise and fall time 6.0 7 13 16 19 ns 2.0 1000 1000 1000 4.5 500 500 500 t r ,t f maximum input rise and fall time 6.0 400 400 400 ns c pd power dissipation capacitance (5) (per package) 136 pf c in maximum input capacitance 5 10 10 10 pf note: 5. c pd determines the no-load dynam ic power consumption, p d = c pd v cc 2 f + i cc v cc , and the no-load dynamic current consumption, i s = c pd v cc f + i cc .
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 6 mm74hc174 ? hex d-type flip-flops with clear ac waveforms t r clock t w t plh t phl t f 90% 90% 50% 50% 10% 10% d input 90% 90% 10% 10% v cc gnd v cc gnd q output 50% 50% v oh v ol figure 3. ac waveform t r clock input t wh t s t wl t f 90% 90% 50% 50% 50% 10% 10% 10% v cc gnd gnd data input 90% 90% 90% 90% 50% 50% 50% 10% 10% 10% 10% t h v cc figure 4. ac waveform
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 7 mm74hc174 ? hex d-type flip-flops with clear physical dimensions x 45 detail a scale: 2:1 8 0 notes: unless otherwise specified a) this package conforms to jedec ms-012, variation ac, issue c. b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash and tie bar protrusions d) conforms to asme y14.5m-1994 e) landpattern standard: soic127p600x175-16am f) drawing file name: m16arev12. seating plane gage plane c c 0.10 see detail a land pattern recommendation pin one n dicator 1 16 8 m 0.25 9 cba b a 5.6 1.27 0.65 1.75 10.00 9.80 8.89 6.00 1.27 (0.30) 0.51 0.35 1.75 max 1.50 1.25 0.25 0.10 0.25 0.19 (1.04) 0.90 0.50 0.36 (r0.10) (r0.10) 0.50 0.25 4.00 3.80 figure 5. 16-lead, small outline integrated circuit (soic) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 8 mm74hc174 ? hex d-type flip-flops with clear physical dimensions 0.65 4.40.1 mtc16rev4 0.11 4.55 5.00 5.000.10 12 7.35 4.45 1.45 5.90 figure 6. 16-lead thin shrink small outline package (tssop) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 9 mm74hc174 ? hex d-type flip-flops with clear physical dimensions 16 9 8 1 notes: unless otherwise specified a this package conforms to jedec ms-001 variation bb b) all dimensions are in millimeters. d) conforms to asme y14.5m-1994 e) drawing file name: n16erev1 19.68 18.66 6.60 6.09 c) dimensions are exclusive of burrs, mold flash, and tie bar protrusions 3.42 3.17 3.81 2.92 (0.40) 2.54 17.78 0.58 0.35 1.78 1.14 5.33 max 0.38 min 8.13 7.62 0.35 0.20 15 0 8.69 a a top view side view figure 7. 16-lead plastic dual-in-line package (pdip) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 1999 fairchild semiconductor corporation www.fairchildsemi.com mm74hc174 ? rev. 1.1.0 10 mm74hc174 ? hex d-type flip-flops with clear
|
